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Packaging Module Development Engineer

Intel · Phoenix, AZtoday
$115k – $189k

BS-level Process Engineering roles on Crosslinked list a median of $112k (529 that show pay).

Develop and optimize semiconductor assembly and packaging processes, equipment, and material specifications

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Worth knowing

Why it is interesting. Shape Intel's packaging technology roadmap, solving reliability challenges for next-generation products

Might not be for you. Focus is on process and equipment optimization, not polymer formulation or materials R&D

Generalist First industry roleBS acceptable

Adjacent materials roleDefine material specifications and collaborate with supply chain and vendor quality teams; evaluate silicon and packaging technologies under heat, humidity, temperature cycles

H-1B filings

Intel filed 974 H-1B labor applications for scientist and engineer roles from Jan to Dec 2025.

Most common titles: Process Engineer, Engineering Manager, Quality Reliability Engineer. Median filed pay: $124K a year.

From U.S. Department of Labor disclosure data. A filing is a record of past hiring, not a promise about this role, so confirm sponsorship with the employer. Titles and filed pay ·Every employer's filings

Seniority
Entry level
Work
On-site
Type
Full-time
Degree
BS
Experience
1+ yrs
Industry
Semiconductor
Role
Process Engineering

Role details

Job Details: Job Description: The Role and Impact Join Intel's Packaging Module Development team and contribute to advancing assembly and packaging technologies critical to Intel's next-generation products. As a Packaging Module Development Engineer, you will design and optimize innovative processes and equipment that enhance manufacturing efficiency, product reliability, and quality. You will play a key role in shaping Intel's technology roadmap by solving complex engineering challenges and delivering industry-leading advancements in packaging solutions.

Business group Intel's Packaging Module Development team focuses on developing cutting-edge assembly and packaging solutions that enable world-class technologies across Intel's diverse product portfolio. This group collaborates with cross-functional teams to optimize manufacturing processes, ensure product reliability, and contribute to Intel's broader mission of driving innovation and technology leadership.

Key Responsibilities

- Develop and optimize assembly processes and equipment to achieve quality, reliability, cost, yield, productivity, and manufacturability goals. - Apply Design of Experiments (DOE) principles and statistical methodologies to refine processes and specifications, documenting improvements through technical reports. - Design and maintain equipment to evaluate silicon and packaging technologies under simulated field conditions, including heat, humidity, temperature cycles, and dynamic forces. - Ensure manufacturability of physical layouts in package design and oversee the lifecycle of manufacturing workflows. - Define material specifications and collaborate with supply chain and vendor quality teams to ensure adherence to performance requirements and standards. - Innovate new techniques, tools, and quality screens to proactively identify and address packaging reliability challenges. - Set reliability benchmarks based on a deep understanding of failure mechanisms, ensuring customer needs are met. - Lead initiatives to solve technical problems and drive continuous improvements across processes and equipment. - Provide technical consultation and collaborate with internal teams and partners to address packaging challenges. - Standardize equipment qualification practices and manufacturing quality systems to align with product milestones and mitigate technical risks.

Qualifications

You must possess the minimum education requirements and minimum required qualifications to be initially considered for this position. Relevant experience can be obtained through schoolwork, classes, project work, internships, and/or military experience. Additional preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications

Bachelor's degree in Mechanical Engineering, Materials Science Engineering, Chemical Engineering, Electrical Engineering, or a related field with 1+ years of relevant experience or Master's degree in Mechanical Engineering, Materials Science Engineering, Chemical Engineering, Electrical Engineering, or a related field. Experience listed above should be a combination of the following: Familiarity with equipment adjustment, process characterization, and manufacturability or electronics assembly.

Preferred Qualifications

Proficiency in Statistical Process Control (SPC) and Design of Experiments (DOE) principles. Hands-on experience in a technology manufacturing environment or semiconductor packaging processes. Demonstrated ability to collaborate with cross-functional teams and contribute to time-sensitive projects. We invite you to apply and bring your expertise, creativity, and passion for innovation to Intel. Be a part of our mission to create world-class packaging solutions and help shape the future of technology.

Job Type: Experienced Hire Shift: Shift 1 (United States of America) Primary Location: US, Arizona, Phoenix Additional Locations: Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Benefits We offer a total compensation package that ranks among the best in the industry.

It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel . Annual Salary Range for jobs which could be performed in the US: $115,110.00-188,890.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role This role will require an on-site presence. • Job posting details (such as work model, location or time type) are subject to change. • ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

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Common questions

What is the salary for the Packaging Module Development Engineer role at Intel?

The listed annual base salary range is $115K–$189K. This figure is taken from the posting itself.

Does Intel sponsor H-1B visas?

Intel has filed H-1B petitions with the US Department of Labor in past years, but this specific posting does not explicitly mention sponsorship for the Packaging Module Development Engineer role. Confirm with the employer before applying if visa support is required.

Where is the Packaging Module Development Engineer role at Intel based?

This role is based in Phoenix, AZ.

What degree is required for the Packaging Module Development Engineer role at Intel?

The posting accepts the following combinations: BS + 1 year, MS + 0 years.

How many years of experience does this Packaging Module Development Engineer role require?

The posting calls for at least 1 years of relevant experience.

What techniques or methods are required for this Packaging Module Development Engineer role?

Design of Experiments (DOE), Statistical Process Control (SPC).