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Substrate Packaging Research and Development Engineer

Intel · Phoenix, AZtodayverified 1 h ago
$134k – $189k

PhD-level Process Engineering roles on Crosslinked list a median of $137k (11 that show pay).

Develop and optimize semiconductor substrate packaging processes, materials, and equipment for high-volume manufacturing.

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Worth knowing

Why it is interesting. Work on heterogeneous integration and die disaggregation, key to Intel's advanced packaging roadmap.

Might not be for you. Heavy focus on sustaining support and high-volume manufacturing, less open-ended R&D.

Mostly at the benchDeep specialist PhD-friendlyFirst industry role

Adjacent materials roleDevelop and optimize advanced packaging processes, materials, and equipment; materials science and material characterization techniques

H-1B filings

Intel filed 974 H-1B labor applications for scientist and engineer roles from Jan to Dec 2025.

Most common titles: Process Engineer, Engineering Manager, Quality Reliability Engineer. Median filed pay: $124K a year.

From U.S. Department of Labor disclosure data. A filing is a record of past hiring, not a promise about this role, so confirm sponsorship with the employer. Titles and filed pay ·Every employer's filings

Seniority
Entry level
Work
Hybrid
Type
Full-time
Degree
PhD
Experience
1+ yrs
Industry
Semiconductor
Role
Process Engineering

Role details

Job Details: Job Description: As a Packaging Module Development Engineer, you will play a vital role in advancing Intel's semiconductor manufacturing capabilities by developing innovative packaging processes and equipment. Your day-to-day responsibilities will focus on optimizing assembly methods to achieve quality, reliability, and efficiency goals in high-volume manufacturing environments. By collaborating with cross-functional teams, you will help shape Intel's next-generation packaging technologies, directly contributing to the company's success in the semiconductor industry.

Business group This position is part of Intel Corporation's Substrate Packaging Technology Development (SPTD) organization, which drives advancements in substrate packaging to support Intel's global technology leadership. The group focuses on delivering next-generation solutions for high-performance and mobile computing applications, enabling heterogeneous integration and die disaggregation across Intel's product portfolio.

Key Responsibilities

Develop and optimize advanced packaging processes, materials, and equipment to meet reliability, quality, and cost targets. Design and implement process specifications, workflows, and equipment configurations for new technologies. Conduct design of experiments (DOE) to characterize process windows and interactions between equipment, materials, and chemistry. Drive continuous improvement efforts to enhance process capability, stability, and productivity. Collaborate with cross-functional teams to resolve technical challenges and deliver impactful solutions. Establish material specifications and partner with suppliers to ensure adherence to performance and quality standards.

Document advancements and process innovations through technical reports and white papers. Provide sustaining support for equipment performance and process health in high-volume manufacturing environments. Behavioral traits: Team Collaboration: Works effectively across cross-functional teams and builds strong partnerships. Comfort with Ambiguity: Thrives in undefined or evolving projects and takes initiative to create direction. Performs Under Pressure: Manages multiple priorities, tight deadlines, and technical challenges while remaining focused on results. Conflict Resolution: Handles disagreements professionally, using data and communication to align stakeholders and reach solutions.

Ownership & Problem Solving: Takes accountability, proactively addresses issues, and drives innovative solutions to completion.

Qualifications

Minimum qualifications

are required to be initially considered for this position.

Preferred qualifications

are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications

PhD degree in Materials Science, Mechanical Engineering, Electrical Engineering, Chemical Engineering, Organic Chemistry, Polymer Engineering, or other similar engineering degree and 1+years of related experience. 1+year of experience in: Combining engineering judgement and data analysis skills to draw conclusions, build models and design experiments. Materials science and engineering, and in material characterization techniques. Knowledge and experience in design of experiments (DOE), statistical data analysis and statistical process control (SPC).

Preferred Qualifications

Working knowledge and/or prior experience in optics and lasers, laser micro-machining and micro-fabrication. Become part of Intel's cutting-edge technology development team, where your expertise and creativity will drive innovation and shape the future of semiconductor manufacturing. Apply today and join us in advancing the boundaries of what's possible.

Job Type: Experienced Hire Shift: Shift 1 (United States of America) Primary Location: US, Arizona, Phoenix Additional Locations: Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Benefits We offer a total compensation package that ranks among the best in the industry.

It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel . Annual Salary Range for jobs which could be performed in the US: $133,800.00-188,890.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. • Job posting details (such as work model, location or time type) are subject to change. • ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment.

If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

Related roles

Common questions

What is the salary for the Substrate Packaging Research and Development Engineer role at Intel?

The listed annual base salary range is $134K–$189K. This figure is taken from the posting itself.

Does Intel sponsor H-1B visas?

Intel has filed H-1B petitions with the US Department of Labor in past years, but this specific posting does not explicitly mention sponsorship for the Substrate Packaging Research and Development Engineer role. Confirm with the employer before applying if visa support is required.

Where is the Substrate Packaging Research and Development Engineer role at Intel based?

This role is based in Phoenix, AZ. Work arrangement: Hybrid.

What degree is required for the Substrate Packaging Research and Development Engineer role at Intel?

This role requires a PhD.

How many years of experience does this Substrate Packaging Research and Development Engineer role require?

The posting calls for at least 1 years of relevant experience.

What techniques or methods are required for this Substrate Packaging Research and Development Engineer role?

design of experiments (DOE), statistical process control (SPC), material characterization.