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CMP Process Engineer

Samsung Semiconductor · Taylor, TX,2d ago,verified 1 h ago
$106k – $145kfrom the posting

BS-level Process Engineering roles on Crosslinked list a median of $115k (771 that show pay).

Optimize CMP process recipes, slurries and pads to control removal rate, uniformity and defects on semiconductor wafers.

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Worth knowing

Why it is interesting. Hands-on slurry and pad evaluation on AMAT/Ebara CMP tools in a high-volume fab

Might not be for you. Fully on-site with possible off-hour or CWW shift work in a fab

Bench and deskDeep specialist Senior hires only

Adjacent materials role:CMP process engineer: slurry and polishing pad evaluation, removal rate control, planarization, dielectric/metal CMP fundamentals

H-1B filings

Samsung Semiconductor filed 3 H-1B labor applications for scientist and engineer roles from Jan to Dec 2025.

Most common titles: Senior Manager, Foundry Customer Engineering, Senior Staff Engineer, Ar/Vr Optics Research, Display Lab, Senior Manager, Customer Quality Engineering. Median filed pay: $188K a year.

From U.S. Department of Labor disclosure data. A filing is a record of past hiring, not a promise about this role, so confirm sponsorship with the employer. Titles and filed pay · Every employer's filings

Seniority
Mid-level
Work
On-site
Type
Full-time
Degree
BS
Experience
5+ yrs
Industry
Semiconductor
Role
Process Engineering
Benefits
onsite cafe and workout facilitiesimmediate 401(k) vestingMBO bonuses

Role details

About Samsung Austin Semiconductor

Samsung is a world leader in advanced semiconductor technology, founded on the belief that the pursuit of excellence creates a better world. At Samsung Austin Semiconductor, we are Innovating Today to Power the Devices of Tomorrow.

Come innovate with us!

Position Summary

A CMP (Chemical Mechanical Polishing) Process Engineer is responsible for the critical semiconductor manufacturing step of planarizing the wafer surface. This is achieved through a synergistic combination of chemical reactions and mechanical force, ensuring that subsequent layers of the chip can be built with high precision. The primary goal of a CMP engineer is to achieve a flat wafer surface by controlling the chemical reaction and mechanical force.

Here's What You'll Be Responsible For

  • Removal Rate (RR) Control: Conducting performance evaluations of various influence factors to ensure the thickness skew before and after CMP is consistent across the entire wafer.
  • Condition Optimization: Determining the optimal process conditions to improve uniformity and resolve chronic issues, such as "center low RR profiles.
  • Recipe Management: Developing and optimizing Recipe (RCP) parameters and improve flatness.
  • Defect & uniformity Management: Managing and improving wafer uniformity and resolving defects such as scratches and particles.
  • Consumable Life Cycle Management: Monitoring the usage cycles of consumables (pads, slurry) to ensure they do not exceed specifications, which could impact quality.
  • Material Evaluation: Evaluating the performance of different slurries and polishing pads to optimize the CMP process.

Basic requirement

  • BS or MS in Chemical, Mechanical, Electrical, or Industrial Engineering, Physics, Chemistry, Material Science, or Computer Science.
  • A minimum 5 years of related experience; Semiconductor Process Flows.
  • Previous experience in a high-volume semiconductor manufacturing environment desired. Applicable manufacturing experience in other industries can be considered.
  • Basic CMP Knowledge: Understanding of dielectric and metal CMP fundamentals, including slurry-pad-conditioning interactions and post-clean steps.
  • Prefer to have some level of Equipment Familiarities: Hands-on experience with major industry CMP tools: AMAT/EBara and their end point systems
  • Data & Statistics: Proficiency in Statistical Process Control (SPC), Fault Detection and Classification (FDC), and analysis software like JMP or Spotfire.
  • Problem Solving: Ability to drive root-cause analysis using methodologies like FMEA, 8D, and first-principles physics approaches.
  • Flexibility: As per business needs, sometimes it is required to work during off-hour times and/or with CWW shift schedule.

Preferred Qualifications

  • Familiar with Metrology Tools: Experience with Ellipsometry, SEM, and AFM for thickness and roughness check.
  • Experience on Defect Reduction: Experience identifying killer defects and improving wafer yield.
  • Basic Idea of Fab Integration: Understanding of how CMP affects following steps (Etch/Photo) and overall yield.
  • DOE: Ability to run structured Design of Experiments for process optimization.

The current base salary range for this role is between $106,000 - $145,000. Individual base pay rates will depend on factors including duties, work location, education, skills, qualifications and experience. Total compensation for this position will include a competitive benefits package and may include participation in company incentive compensation programs, which are based on factors to include organizational and individual performance. This position may include access to controlled information or technology under U.S. export control laws. Employment may be contingent on either the applicant verifying that the applicant falls under the “U.S.

Person” definition (including U.S. citizens, U.S. lawful permanent residents, and those granted U.S. asylum or refugee status) or the employer timely obtaining any necessary export license under federal law. The employer evaluates export licensing on a case-by-case basis and may decline to proceed with a job applicant in its sole discretion, as export license applications can take many weeks to process.

Total Rewards

At Samsung Austin Semiconductor, base pay is just one part of our total compensation package. The base compensation for this role will depend on education, experience, skills, and location.

We offer a comprehensive benefits package, including:

  • Medical, dental, and vision insurance
  • Life insurance and 401(k) matching with immediate vesting
  • Onsite café(s) and workout facilities
  • Paid maternity and paternity leave
  • Paid time off (PTO) + 2 personal holidays and 10 regular holidays
  • Wellness incentives and MORE

Eligible full-time employees (salaried or hourly) may also receive MBO bonuses based on company, division, and individual performance.

All positions at Samsung Austin Semiconductor are full-time on-site.

Trade Secrets

By submitting an application, you agree not to disclose to Samsung or induce or encourage Samsung to use any confidential or proprietary information (including trade secrets) belonging to a current or former employer or other entity.

  • Please visit Samsung membership to see Privacy Policy, which defaults according to your location. You can change Country/Language at the bottom of the page. If you are European Economic Resident, please click here.
  • Samsung Electronics America, Inc. and its subsidiaries are committed to Equal Employment Opportunity for all individuals regardless of race, color, religion, gender, age, national origin, marital status, sexual orientation, gender identity, status as a protected veteran, genetic information, status as a qualified individual with a disability, or any other characteristic protected by law.

Related roles

Common questions

What is the salary for the CMP Process Engineer role at Samsung Semiconductor?

The listed annual base salary range is $106K–$145K. This figure is taken from the posting itself.

Does Samsung Semiconductor sponsor H-1B visas?

Samsung Semiconductor has filed H-1B petitions with the US Department of Labor in past years, but this specific posting does not explicitly mention sponsorship for the CMP Process Engineer role. Confirm with the employer before applying if visa support is required.

Where is the CMP Process Engineer role at Samsung Semiconductor based?

This role is based in Taylor, TX.

What degree is required for the CMP Process Engineer role at Samsung Semiconductor?

This role asks for a bachelor's degree.

How many years of experience does this CMP Process Engineer role require?

The posting calls for at least 5 years of relevant experience.

What polymers or materials does this CMP Process Engineer role work with?

CMP slurries, polishing pads, dielectric films, metal films.

What techniques or methods are required for this CMP Process Engineer role?

SPC, FDC, FMEA, 8D root-cause analysis.