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Staff Engineer – Microelectronics Packaging Technology

TTM Technologies · Syracuse, NYtodayverified 1 h ago
$101k – $178kfrom the posting

BS-level R&D / Research roles on Crosslinked list a median of $126k (444 that show pay).

Design and simulate heterogeneously integrated SiP microelectronics packages, including materials and reliability analysis.

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Worth knowing

Why it is interesting. Work across full technology development cycle from early TRLs to manufacturing readiness on cutting-edge microelectronics packaging.

Might not be for you. Requires 9+ years experience and 6-7 years hands-on semiconductor packaging—not for early-career.

Deep specialist Senior hires only

Adjacent materials rolepackaging elements such as substrate technologies, silicon interconnects, and metallurgy, underfills, epoxies, thermal interface materials

Seniority
Staff/Principal
Work
On-site
Type
Full-time
Degree
BS
Experience
9+ yrs
Industry
Electronics
Role
R&D / Research
Clearance
Ability to obtain

Role details

TTM Technologies, Inc. – Publicly Traded US Company, NASDAQ (TTMI) – Top-5 Global Printed Circuit Board Manufacturer

About TTM

TTM Technologies, Inc. is a leading global manufacturer of technology products, including mission systems, radio frequency (“RF”) components, RF microwave/microelectronic assemblies, and technologically advanced printed circuit boards (“PCB”s). TTM stands for time-to-market, representing how TTM's time-critical, one-stop design, engineering and manufacturing services enable customers to reduce the time required to develop new products and bring them to market.

Additional information can be found at www.ttm.com

*Position Summary:*

As a Staff Engineer – Microelectronics Packaging Technology, you will be part of a multidisciplinary advanced technology team developing highly integrated System-In-Packages (SiP) and module sub-systems for Aerospace, Defense, Industrial, medical use cases. You will be an individual contributor with subject matter expertise to design and layout heterogeneously integrated SiP packages, analyze thermal and mechanical behavior, and support development of SiP design infrastructure. This is an excellent opportunity to work across full spectrum of technology development cycle from conceptualization (early TRLs) to manufacturing readiness (mid-MRLs)

This role calls for an individual to provide in-depth engineering analysis, model-based engineering problem solving, and collaborate cross-functionally. You will interface closely with teams across internal manufacturing, operations, business units, external material suppliers, and process vendors. The successful candidate will foster technology-driven thinking for differentiation, but manufacturing-informed for design packaging solutions.

*Role’s Responsibilities:*

  • Lead the design and development of advanced SiPs and module package solutions using 2D/3D packaging technologies with 50micron to 130micron flip-chip interconnects, WLP bumped die, and embedded die.
  • Provide technical leadership in support of package architecture selection by generating 3D package designs, manufacturability, and risk assessments.
  • Generate and optimize detailed package designs in 3D environment using SOLIDWORKS. This will be done in collaborate with RF/MW/electrical engineering teams
  • Perform complex physics-based mechanical and vibration simulations for SiP configurations using FEM tools (ANSYS) to analyze chip-package interaction, package-board interaction, warpage, stress, and reliability risks.
  • Perform SiP-level thermal simulations for microelectronics packages using FEM tools (ANSYS)
  • Define and assist in the buildup of SiP design infrastructure that includes package design flows, 3D modeling and simulation methodologies, generating package design rules.
  • Lead or assist in writing white papers, technical proposals, and conference publications.
  • Benchmark industry best practices and evaluate emerging technologies for package design, assembly materials, and process innovations.
  • Perform and collate tradeoff analysis on ambiguous problems that considers interdisciplinary nature of semiconductor packages.
  • Communicate complex technical concepts effectively to cross-functional project teams, operations, suppliers, business teams
  • Be creative in designing and developing innovative integration methods that foster the spirit of differentiation and generation of IPs
  • Assist in project management by providing planning inputs for defining packaging tasks, schedule, and cost.

Job Knowledge, Skills, Abilities

  • Must possess a strong knowledge across broad spectrum of packaging technology landscape from component packaging to heterogeneously integrated SiPs.
  • Must possess good understanding in various packaging elements such as substrate technologies, silicon interconnects, and metallurgy, underfills, epoxies, thermal interface materials, isolating shielding, assembly processes.
  • Demonstrate strong understanding in the interdisciplinary nature of packaging by articulating packaging materials behaviors as related to their mechanical, thermal, electrical characteristics, and manufacturability.
  • Must have advanced skills in 3D modeling (e.g., SOLIDWORKS) and FEA-based analysis (e.g., ANSYS) for mechanical and thermals. Exposure to basic vibration analysis concepts will be an added advantage.
  • Demonstrate ability to optimize package designs and resolve design issues using structured problem-solving techniques based on physics (mathematical models) and/or statistics (DOEs).
  • Make balanced engineering decisions for ambiguous problems using structured tradeoff analysis that related to objective goals.
  • Ability to collate information with appropriate supporting data and present into a coherent report for communication and distribution.

*Education and Experience*

  • Bachelor’s degree in mechanical engineering, that includes material’s coursework. Master’s education will be a plus
  • Minimum 9+ Years Relevant Experience
  • 6 to 7 years of hands-on semiconductor packaging development experience

Must have a background that would permit the U.S. Department of Defense to issue a Secret clearance when necessary for work on a project that requires such a clearance.

*Compensation and Benefits:*

TTM offers a variety of health and well-being benefit programs. Benefit options include medical, dental, vision, 401k, flexible spending and health savings accounts, accident benefits, life insurance, disability benefits, paid vacation & holidays. Benefits are available on the 1st of the month following date of hire. For some positions, only PTO and holiday benefits are offered.

Compensation ranges for roles at TTM Technologies varies depending on a wide array of factors that are considered in making compensation decisions including but not limited to skill sets; experience and training; certifications; and other business and organizational needs. The disclosed range estimate has not been adjusted for the applicable geographic differential associated with the location at which the position may be filled. At TTM Technologies, it is not typical for an individual to be hired at or near the top of the range for their role and compensation decisions are dependent on each individual set of circumstances. A reasonable estimate of the current range is:

$101,361 - $178,255

Additional compensation: An annual or quarterly company bonus may apply based on position assignment. Positions hired for alternative shift may be eligible for a shift premium based on the assigned shift and location.

*Export Statement:*

Must comply with TTM Export Control Policies and Procedures and all applicable laws including ITAR, EAR and OFAC including but not limited to: a) being able to identify ITAR product on the manufacturing floor and understand that access to these products and related technical data is restricted to only US Citizens and US Permanent Residents; b) recognition of Foreign Person visitors by badge differentiation; c) understand and follow authorization procedures for bringing foreign visitors into facilities (VAL); d) understand the Export and ITAR requirements for shipments leaving the US; e) manage vendor approvals for ITAR manufacturing and services.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, citizenship, disability or protected veteran status.

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Common questions

What is the salary for the Staff Engineer – Microelectronics Packaging Technology role at TTM Technologies?

The listed annual base salary range is $101K–$178K. This figure is taken from the posting itself.

Does TTM Technologies sponsor H-1B visas?

TTM Technologies has filed H-1B petitions with the US Department of Labor in past years, but this specific posting does not explicitly mention sponsorship for the Staff Engineer – Microelectronics Packaging Technology role. Confirm with the employer before applying if visa support is required.

Where is the Staff Engineer – Microelectronics Packaging Technology role at TTM Technologies based?

This role is based in Syracuse, NY.

What degree is required for the Staff Engineer – Microelectronics Packaging Technology role at TTM Technologies?

This role requires a BS.

How many years of experience does this Staff Engineer – Microelectronics Packaging Technology role require?

The posting calls for at least 9 years of relevant experience.

What polymers or materials does this Staff Engineer – Microelectronics Packaging Technology role work with?

underfills, epoxies, thermal interface materials, metallurgy.

What techniques or methods are required for this Staff Engineer – Microelectronics Packaging Technology role?

FEA (ANSYS), thermal simulation, vibration analysis.