Quantum Interposer Integration Engineer
BS-level Process Engineering roles on Crosslinked list a median of $112k (610 that show pay). This posting does not list pay.
Integrate and optimize wafer-level process flows for superconducting quantum interposers
Worth knowing
Why it is interesting. Hands-on ownership of deposition, etch, lithography and wafer bonding for quantum hardware at IBM Research.
Might not be for you. Requires 7+ years semiconductor process experience and deep silicon-spin interposer background — not an entry point.
Adjacent materials rolesuperconducting interposers, deposition (PVD/CVD), etch, lithography, wafer bonding, indium bumping, gold thermocompression
H-1B filings
IBM filed 3 H-1B labor applications for scientist and engineer roles from Jan to Dec 2025.
Most common titles: Hardware Development Engineer, Packaging Development Engineering Manager, Industrial Engineer. Median filed pay: $195K a year.
From U.S. Department of Labor disclosure data. A filing is a record of past hiring, not a promise about this role, so confirm sponsorship with the employer. Titles and filed pay ·Every employer's filings
- Seniority
- Senior
- Work
- On-site
- Type
- Full-time
- Degree
- BS
- Experience
- 7+ yrs
- Industry
- Semiconductor
- Role
- Process Engineering
Role details
Introduction
At IBM Research, we are the innovation engine of IBM. Exploring what’s next in computing and shaping the technologies the world will rely on tomorrow. From advancing AI and hybrid cloud to pioneering practical quantum computing, we anticipate challenges and unlock new opportunities for clients, partners, and society. Working in Research means joining a team that accelerates discovery at the intersection of high-performance computing, AI, quantum, and cloud. You’ll collaborate with leading scientists, engineers, and visionaries to push boundaries and turn ideas into reality.
With a culture built on curiosity, creativity, and collaboration, IBM Research offers the opportunity to grow your career while contributing to breakthroughs that transform industries and change the world.
Your Role And Responsibilities
As a Silicon spin Interposer Process Integration Engineer, you will be responsible for integrating, optimizing, and sustaining end‑to‑end process flows required to manufacture superconducting interposers and advanced wafer‑level components in support of IBM’s silicon spin quantum computing efforts. This role is highly cross‑functional, requiring stronger hands‑on engagement with deposition, etch, lithography, bonding, and finishing technologies, along with the ability to characterize and model complex process flows for performance, yield, and throughput.
You will collaborate closely with senior technical leadership and proactively coordinate with fabrication, metrology, and packaging teams to ensure stable, scalable, high‑quality manufacturing performance.
Essential Duties
- Collaborate with wafer‑level manufacturing teams to refine, mature, and technically guide superconducting interposer wafer flows.
- Develop, integrate, and refine post‑process flows for superconducting interposers, including deposition, etching, planarization, lithography, wafer dicing, and surface finishing.
- Selection of equipment and processes, and guiding the process of installing, qualifying and operating the required processes.
- Support and optimize various wafer bonding technologies and associated process flows to meet electrical, mechanical, and cryogenic performance targets.
- Develop advanced processes for shaping and finishing interposer components, enabling novel architectures and topologies.
- Perform process modeling and yield analysis to identify bottlenecks, optimize throughput, plan for tool utilization, and enhance overall manufacturing efficiency.
- Conduct hands‑on characterization and structured experimentation to validate process interactions, assess materials behavior, and drive resolution of integration‑related issues.
- Partner with metrology teams to define measurement plans, analyze data, and correlate process parameters with device‑level performance and yield.
- Collaborate with design, packaging, and manufacturing engineers to ensure process compatibility, cross‑team alignment, and timely execution against development and production milestones.
- Support documentation of process flows, integration strategies, equipment capability requirements, and troubleshooting methodologies.
- Communicate progress, risks, and key technical findings to senior management and provide coordination across cross‑functional engineering teams.
Preferred Education
Doctorate Degree
Required Technical And Professional Expertise
- BS, MS, or PhD in Electrical Engineering, Physics, Chemistry, Materials Science, or a related field with 7+ years of relevant experience.
- Experience with silicon spin interposer technologies.
- Hands‑on experience with semiconductor or advanced packaging manufacturing processes, including deposition (PVD/CVD), etch, lithography, wafer bonding, and post‑processing/finishing.
- Familiarity with bonding technologies such as indium bumping, gold thermocompression, solder‑based interconnects, or direct‑bonding approaches.
- Experience with process flow modeling, yield modeling, and manufacturing planning for throughput, downtime, and capital utilization.
Preferred Technical And Professional Experience
- Strong analytical and problem‑solving skills, with the ability to conduct structured experiments and interpret complex data sets.
- Clear communication skills with experience interfacing with senior leadership and coordinating across cross‑functional engineering teams.
- Proficiency with statistical analysis tools (e.g., JMP) and Design of Experiments (DOE) methodologies
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