Mechanical Stress Simulation Staff Engineer
BS-level R&D / Research roles on Crosslinked list a median of $128k (386 that show pay). This posting does not list pay.
Run multi-level mechanical stress simulations of semiconductor packaging and BEOL layers, and plan material-property test structures.
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Why it is interesting. Combines FEA with material-property test-structure design for BEOL and heterogeneous integration reliability.
Might not be for you. Mostly computational simulation work, with limited hands-on materials synthesis or formulation.
Adjacent materials role:Simulate viscoelastic/crack/delamination behavior in BEOL layers; plan test structures to characterize bulk/shear modulus, CTE, binding strength; BEOL materials familiarity
- Seniority
- Staff/Principal
- Work
- On-site
- Type
- Full-time
- Degree
- BS
- Experience
- 3+ yrs
- Industry
- Semiconductor
- Role
- R&D / Research
Role details
SkyWater is hiring a Mechanical Stress Simulation Staff Engineer to be responsible for executing advanced mechanical stress simulations for semiconductor advanced packaging, heterogeneous integration, and BEOL (Back-End-Of-Line) metallization layers. This role leverages industry-leading software tools to model, analyze, and optimize mechanical and thermal behaviors in complex semiconductor structures, ensuring reliability and performance across device, die, chip, and package levels.
Key Responsibilities
Develop and execute multi-level mechanical stress models for semiconductor devices, circuits, dies, chips, and packaging. Simulate elastic, viscoelastic, and crack-related phenomena, including recoverable stress/strain, plastic deformation, delamination, and crack propagation, with direct impact on device performance and BEOL reliability. Utilize advanced simulation software such as ANSYS, TCAD Sentaurus, SInterconnect, and MultiPhysics Fusion to analyze mechanical stress, heat transfer, and dissipation in semiconductor packaging and BEOL layers.
Plan test structures to characterize material properties (bulk modulus, shear modulus, coefficient of thermal expansion, binding strength) required for simulation and reproducing shortloop experiments. Collaborate with process integration teams to utilize simulation results in design and manufacturing workflows. Document methodologies, results, and recommendations for reliability improvements and yield enhancement. Required Skills & Qualifications: Bachelor’s or Master’s degree in Mechanical Engineering, Materials Science, or a related field with 3+ years of related experience. Experience with crack/delamination analysis and BEOL processes/materials.
Proficiency in finite element analysis (FEA) and simulation methodologies. Hands-on expertise with mechanical simulation tools (ANSYS, Sentaurus, MultiPhysics Fusion, AutoCAD, SolidWorks). Familiarity with semiconductor packaging systems and BEOL materials. Strong analytical, problem-solving, and communication skills. Preferred Experience: Prior work in semiconductor industry, especially in packaging and BEOL. Knowledge of device performance impacts due to mechanical stress. Experience with characterization of material properties and shortloop experimental validation. Semiconductor technology integration experience #SW2
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