SPSr. Silicon Packaging Process Engineer, Silicon Technology (Starlink)
BS-level Process Engineering roles on Crosslinked list a median of $113k (687 that show pay). This posting does not list pay.
Own semiconductor packaging assembly processes from concept to mass production for Starlink ICs
Worth knowing
Why it is interesting. Vertical integration of IC packaging at SpaceX — build the assembly line from scratch for the world's largest satellite constellation
Might not be for you. Heavy focus on semiconductor packaging equipment and process, not polymer formulation or materials R&D
Adjacent materials roleOwn packaging assembly processes... wafer grinding, wafer dicing, lithography, lamination, plating, etching, SMT, flip chip, bonding, molding, underfill, dispense, sputter, lid attach
H-1B filings
SpaceX filed 7 H-1B labor applications for scientist and engineer roles from Jan to Dec 2025.
Most common titles: Senior Build Engineer, Starlink Engineer, Propulsion Engineer II. Median filed pay: $120K a year.
From U.S. Department of Labor disclosure data. A filing is a record of past hiring, not a promise about this role, so confirm sponsorship with the employer. Titles and filed pay ·Every employer's filings
- Seniority
- Senior
- Work
- On-site
- Type
- Full-time
- Degree
- BS
- Experience
- 5+ yrs
- Industry
- Telecommunications
- Role
- Process Engineering
Role details
SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars.
SR. SILICON PACKAGING PROCESS ENGINEER, SILICON TECHNOLOGY (STARLINK) SpaceX is leveraging its experience in building rockets and spacecraft to deploy Starlink, the world’s most advanced broadband internet system. Starlink is the world’s largest satellite constellation and is providing fast, reliable internet to 4M+ users worldwide. We design, build, test, and operate all parts of the system – thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We’ve only begun to scratch the surface of Starlink’s potential global impact.
As we continue to upgrade and expand the constellation, we’re looking for best-in-class engineers to join the team.
In true SpaceX fashion, Starlink is taking the next step in vertical integration by bringing integrated circuit packaging and assembly in-house for development and manufacturing. We are looking for hands-on and dynamic engineers with expertise in semiconductor packaging design, process development, equipment, and test. You will assume full ownership of packaging products and process modules and take them from concept to mass production as we strive to make Starlink more affordable to those who need it most.
Responsibilities
- Own packaging assembly processes from concept to mass production including equipment and material selection for wafer-level and chip-level systems
- Develop new technologies and establish baselines for assembly and packaging including wafer grinding, wafer dicing, lithography, lamination, plating, etching, SMT, flip chip, bonding, molding, underfill, dispense, sputter, lid attach, and solder ball attach
- Bring-up for new product introduction (NPI) and new technology introduction (NTI) for assembly packaging lines
- Own packaging prototypes, product development and release to production
- Select equipment and material to meet quality, reliability, cost, yield, and production targets
- Interface with equipment and material suppliers including continuous improvement plans, cost reduction, and productivity improvements
- Cross-functional interface with IC design, materials, thermal, systems, and production teams
- Implement advanced packaging solutions into SpaceX next generation products
Basic Qualifications
- Bachelor’s degree in electrical engineering, mechanical engineering, chemical engineering, materials science, physics, or other applied engineering discipline
- 5+ years of professional experience in semiconductor assembly and packaging
Preferred Skills And Experience
- Advanced technical degree
- 7+ years industry experience with microelectronics packaging development
- Packaging familiarity with flip-chip, BGA, fcCSP, WLCSP, fan out FO processes, system-in-package SiP, multi-chip modules MCM, panel level packaging, heterogenous and chiplet integration
- Hands-on packaging, PCB, PCBA, or SMT assembly experience
- OSAT (outsource semiconductor assembly and test) experience a plus
Itar Requirements
- To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C.
- 1157, or (iv) Asylee under 8 U.S.C.
- 1158, or be eligible to obtain the required authorizations from the U.S. Department of State. Learn more about the ITAR here.
SpaceX is an Equal Opportunity Employer; employment with SpaceX is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.
Applicants wishing to view a copy of SpaceX’s Affirmative Action Plan for veterans and individuals with disabilities, or applicants requiring reasonable accommodation to the application/interview process should reach out to [email protected] *.*
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