Packaging Engineering Intern MS/PhD
MS-level Product Development roles on Crosslinked list a median of $161k (12 that show pay). This posting does not list pay.
Support design, development and characterization of semiconductor packaging technologies (wirebond, flip chip, modules, SIPs) on cross-functional teams.
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Worth knowing
Why it is interesting. Exposure to a broad range of package types (wirebond, flip chip, modules, SiPs) with materials, thermal and electrical characterization.
Might not be for you. Materials work is only one thread; the role leans toward general package engineering and design.
Adjacent materials rolePackaging advancements with "material, mechanical, thermal, and electrical characterization"; prefers thin film deposition, plating, adhesion, surface treatment experience
H-1B filings
Texas Instruments filed 38 H-1B labor applications for scientist and engineer roles from Jan to Dec 2025.
Most common titles: Validation Engineering Manager, Analog Design Manager, Digital Design Manager. Median filed pay: $166K a year.
From U.S. Department of Labor disclosure data. A filing is a record of past hiring, not a promise about this role, so confirm sponsorship with the employer. Titles and filed pay ·Every employer's filings
- Seniority
- Intern/Co-op
- Work
- On-site
- Type
- Internship
- Degree
- MS
- Experience
- 0+ yrs
- Industry
- Semiconductor
- Role
- Product Development
Role details
Change the world. Love your job. Interface across various work areas and organizations to help with the design, development, and analysis of different semiconductor packaging technologies to enable differentiation for TI's analog and embedded processing products. Assignments may include participation in cross-functional teams to develop internal and external solutions for semiconductor packaging technologies, including Wirebond, Flip Chip, Modules, SIPs and other advanced packages at different stages of readiness. Cultivate packaging advancements with work in material, mechanical, thermal, and electrical characterization.
TI's innovative packaging technologies are designed to solve customers' problems by delivering advances in miniaturization, integration, high reliability, high performance, and low power. Put your talent to work with us as a Packaging Engineering Intern ! Minimum Requirements: Currently pursuing a Masters degree in Mechanical Engineering, Materials Science, Chemical Engineering, Optical Science, Electrical Engineering or related.
Cumulative 3.0/4.0 GPA or higher Preferred Qualifications: Coursework or research in semiconductor packaging/fabrication Experience with AutoCAD design and FEM modeling Strong fundamentals in heat transfer, thermodynamics, and stress analysis Experience with Semiconductor MEMS/3D integration design and fabrication Project experience in the areas of: CVD, PVD, thin film deposition, electroplating, plasma etch, ML based package design, wafer bumping, or optical packaging Experience with plating, adhesion, surface treatment process Hands experience with semiconductor fabrication and characterization tools including VI Scopes, X-ray Inspection, materials characterization, and FA techniques Strong written and verbal communication skills Demonstrated analytical and problem solving skills Ability to work in teams and collaborate effectively with people in different functions Strong time management skills that enable on-time project delivery Ability to build strong, influential relationships Ability to work effectively in a fast-paced and rapidly changing environment Ability to take the initiative and drive for results
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