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TI

Career Accelerator Program - Packaging Engineer - PhD

Texas Instruments · Santa Clara, CAtoday

Design and develop semiconductor packaging technologies and downselect packaging materials within TI's 12-month new-grad program.

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Worth knowing

Why it is interesting. 12-month accelerator program with technical training, working on wirebond, flip chip and SiP packaging for TI's analog products

Might not be for you. Packaging design and modeling focus, with materials selection as one part rather than the core

GeneralistFast-paced PhD-friendlyFirst industry role

Adjacent materials roleDirect design-of-experiments and work with material suppliers to downselect innovative packaging materials; PhD in Material Science; plating, adhesion, thin film deposition

H-1B filings

Texas Instruments filed 38 H-1B labor applications for scientist and engineer roles from Jan to Dec 2025.

Most common titles: Validation Engineering Manager, Analog Design Manager, Digital Design Manager. Median filed pay: $166K a year.

From U.S. Department of Labor disclosure data. A filing is a record of past hiring, not a promise about this role, so confirm sponsorship with the employer. Titles and filed pay ·Every employer's filings

Seniority
Entry level
Work
On-site
Type
Full-time
Degree
PhD
Experience
0+ yrs
Industry
Semiconductor
Role
Product Development

Role details

Change the world. Love your job. In your first year with TI, you will participate in the Career Accelerator Program (CAP), which provides professional and technical training and resources to accelerate your ramp into TI, and set you up for long-term career success. Within this program, we also offer function-specific technical training and on-the-job learning opportunities that will encourage you to solve problems through a variety of hands-on, meaningful experiences from your very first day on the job. The TMG Development program is a 12-month program for new college graduates in the TMG organization.

Interface across various work areas and organizations to help with the design, development and analysis of different semiconductor packaging technologies to enable differentiation for TI's analog and embedded processing products. TI's innovative packaging technologies are designed to solve customers' problems by delivering advances in miniaturization, integration, high reliability, high performance, and low power. In this role you'll get the opportunity to thrive in a fast paced, dynamic environment where high-energy, prioritization skills and adaptability are a must!

Packaging engineers play an important role at TI which encompasses the following responsibilities: Partner with the businesses to design and develop internal and external solutions for semiconductor packaging technologies, including Wirebond, Flip Chip, Modules, SIPs and other advanced packages at different stages of readiness Participate in cross-functional teams, supporting product qualification and production, helping to meet reliability and yield requirements, design testability, and test coverage Direct design-of-experiments and work with material suppliers to downselect innovative packaging materials to enhance the reliability and performance of advanced packages.

Conduct electrical, mechanical, thermal models to comprehend silicon-to-package interaction, establish design rules, and to predict and prevent the use of high risk designs. As a Packaging engineer you will enjoy an environment of smart collaboration with a global team of the industry's top engineering minds at your disposal. TI's corporate culture is one of competitive spirit which fuels continued business growth and constant career opportunities. While ethical business practice is a central aspect of the work place-you will be treated with respect, dignity, kindness and courtesy. Put your talent to work with us as a Packaging engineer !

Minimum Requirements: PhD in Material Science, Mechanical Engineering, Chemical Engineering, Materials Science, Physics, Electrical Engineering, or related Cumulative 3.0/4.0 GPA or higher Preferred Qualifications: Coursework or research in semiconductor packaging/fabrication Experience with AutoCAD design and FEM modeling Strong fundamentals in heat transfer, thermodynamics, and stress analysis Experience with Semiconductor MEMS/3D integration design and fabrication Project experience in the areas of: CVD, PVD, thin film deposition, electroplating, plasma etch, ML based package design, wafer bumping, or optical packaging Experience with plating, adhesion, surface treatment process Hands experience with semiconductor fabrication and characterization tools including VI Scopes, X-ray Inspection, materials characterization, and FA techniques Strong written and verbal communication skills Demonstrated analytical and problem solving skills Ability to work in teams and collaborate effectively with people in different functions Strong time management skills that enable on-time project delivery Ability to build strong, influential relationships Ability to work effectively in a fast-paced and rapidly changing environment Ability to take the initiative and drive for results

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Common questions

Does Texas Instruments sponsor H-1B visas?

Texas Instruments has filed H-1B petitions with the US Department of Labor in past years, but this specific posting does not explicitly mention sponsorship for the Career Accelerator Program - Packaging Engineer - PhD role. Confirm with the employer before applying if visa support is required.

Where is the Career Accelerator Program - Packaging Engineer - PhD role at Texas Instruments based?

This role is based in Santa Clara, CA.

What degree is required for the Career Accelerator Program - Packaging Engineer - PhD role at Texas Instruments?

This role requires a PhD.

How many years of experience does this Career Accelerator Program - Packaging Engineer - PhD role require?

The posting calls for at least 0 years of relevant experience.

What techniques or methods are required for this Career Accelerator Program - Packaging Engineer - PhD role?

X-ray inspection, materials characterization, failure analysis, VI scope testing.